RISC-V International Specifications
RISC-V
Every RISC-V CPU implements ratified ISA modules from riscv.org/specifications — the open alternative to ARM/x86 ISAs.
What It Is
Open ISA specifications: base integer, extensions (M, A, F, D, C, V, B…), privileged architecture, and ratified profile definitions.
Taxonomy
By status: Ratified · Frozen · Draft · By extension letter · Profiles (RVA20, RVA22…)
Top-Level Categories
Master Catalog
Sub-Indexes & Guides
Non-profit global organization that owns and maintains the open, royalty-free RISC-V ISA. Publishes the Unprivileged ISA (base integer and extensions), Privileged Architecture, and ABI/psABI specifications. Members include Google, NVIDIA, Qualcomm, Western Digital, and hundreds of academic and commercial organizations.
View all bodies →Curated specs from RISC-V
RISC-V is the only fully open, royalty-free ISA gaining mainstream adoption — in SiFive/StarFive SoCs, SSD controllers, RISC-V Linux, and embedded MCUs. The base spec is required reading for anyone doing hardware or firmware on RISC-V.
Required for any OS kernel, hypervisor, or firmware work on RISC-V. Every RISC-V Linux port, OpenSBI, U-Boot, QEMU model, and Keystone security monitor implements this spec.
Required for writing RISC-V assembly, setting up cross-compilation toolchains, or building compilers and OSes targeting RISC-V.