RISC-V Privileged Architecture
Required for any OS kernel, hypervisor, or firmware work on RISC-V. Every RISC-V Linux port, OpenSBI, U-Boot, QEMU model, and Keystone security monitor implements this spec.
What It Defines
Defines the M-mode (machine), S-mode (supervisor), and U-mode (user) privilege levels, control and status registers (CSRs), physical memory protection (PMP), interrupt and trap handling, trap delegation, the Hypervisor extension (H), and the SBI (Supervisor Binary Interface) used by RISC-V operating systems, hypervisors, and firmware.
Canonical (Normative)
Related References
Non-profit global organization that owns and maintains the open, royalty-free RISC-V ISA. Publishes the Unprivileged ISA (base integer and extensions), Privileged Architecture, and ABI/psABI specifications. Members include Google, NVIDIA, Qualcomm, Western Digital, and hundreds of academic and commercial organizations.
Related Specs
RISC-V is the only fully open, royalty-free ISA gaining mainstream adoption — in SiFive/StarFive SoCs, SSD controllers, RISC-V Linux, and embedded MCUs. The base spec is required reading for anyone doing hardware or firmware on RISC-V.
Required for writing RISC-V assembly, setting up cross-compilation toolchains, or building compilers and OSes targeting RISC-V.
Every modern x86-64 and AArch64 server, workstation, and PC uses UEFI. Required for OS development, bootloader work (GRUB, systemd-boot, shim), Secure Boot policy, and firmware engineering.
ACPI is how every OS discovers hardware topology, manages CPU power states, handles thermal throttling, and receives platform events. Required for kernel, power management, and firmware development on all modern x86/Arm platforms.