RISC-V Unprivileged ISA
RISC-V is the only fully open, royalty-free ISA gaining mainstream adoption — in SiFive/StarFive SoCs, SSD controllers, RISC-V Linux, and embedded MCUs. The base spec is required reading for anyone doing hardware or firmware on RISC-V.
What It Defines
Defines the base integer instruction sets (RV32I, RV64I) and standard extensions (M multiply/divide, A atomics, F/D floating-point, C compressed, V vector, B bit-manipulation) of the open RISC-V ISA. Covers registers, instruction encodings, memory model (RVWMO weak ordering), and the modular extension framework used by all RISC-V implementations.
Canonical (Normative)
Convenient (Practical)
Related References
Non-profit global organization that owns and maintains the open, royalty-free RISC-V ISA. Publishes the Unprivileged ISA (base integer and extensions), Privileged Architecture, and ABI/psABI specifications. Members include Google, NVIDIA, Qualcomm, Western Digital, and hundreds of academic and commercial organizations.
Related Specs
Required for any OS kernel, hypervisor, or firmware work on RISC-V. Every RISC-V Linux port, OpenSBI, U-Boot, QEMU model, and Keystone security monitor implements this spec.
Required for writing RISC-V assembly, setting up cross-compilation toolchains, or building compilers and OSes targeting RISC-V.
Every compiled binary on Linux is ELF. Understanding ELF is essential for debugging, reverse engineering, dynamic linking, build toolchains, binary patching, and tools like readelf, objdump, ldd, and patchelf.