Arm Architecture Reference Manual (AArch64)
AArch64 now dominates mobile (every smartphone), Apple Silicon (M-series Macs, iPad), and increasingly servers (AWS Graviton3/4, Ampere Altra, Neoverse). Cross-compilation, performance tuning, and assembly work all require knowing the ISA.
What It Defines
The definitive reference for the 64-bit Arm ISA (A-profile). Covers A64 instructions, system registers (EL0–EL3 exception levels), the memory model (weak ordering, LSE atomics, MTE memory tagging), SVE/SVE2 scalable vector extensions, the Pointer Authentication and Branch Target Identification (PAC/BTI) security extensions, and the complete exception/interrupt model.
Canonical (Normative)
Convenient (Practical)
Related References
Designs and licenses the Arm CPU architectures used in virtually all mobile, embedded, and increasingly server and desktop processors. Publishes the Architecture Reference Manual (ARM), Arm Architecture Procedure Call Standard (AAPCS), and related ABI specifications. The AArch64 (64-bit Arm) architecture powers Apple Silicon, AWS Graviton, Qualcomm Snapdragon, and Android devices.
Related Specs
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