Arm Architecture Procedure Call Standard (AArch64)
Every function call on AArch64 (Apple Silicon, Android arm64, AWS Graviton) follows AAPCS64. Required for correct assembly, FFI bindings from any language, and compiler backend targeting Arm64.
What It Defines
Defines the calling conventions for 64-bit Arm code: general-purpose register roles (x0–x7 for integer args/results, x8 indirect result, x9–x15 caller-saved, x19–x28 callee-saved, x29 frame pointer, x30 link register), floating-point and SIMD register conventions, Homogeneous Floating-point/Vector Aggregate (HFA/HVA) passing, and stack alignment requirements.
Canonical (Normative)
Convenient (Practical)
Designs and licenses the Arm CPU architectures used in virtually all mobile, embedded, and increasingly server and desktop processors. Publishes the Architecture Reference Manual (ARM), Arm Architecture Procedure Call Standard (AAPCS), and related ABI specifications. The AArch64 (64-bit Arm) architecture powers Apple Silicon, AWS Graviton, Qualcomm Snapdragon, and Android devices.
Related Specs
AArch64 now dominates mobile (every smartphone), Apple Silicon (M-series Macs, iPad), and increasingly servers (AWS Graviton3/4, Ampere Altra, Neoverse). Cross-compilation, performance tuning, and assembly work all require knowing the ISA.
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