PCI Express (PCIe) Base Specification
PCIe is the universal high-speed peripheral bus. Understanding lane width, bandwidth, BAR mapping, and MMIO is essential for GPU compute (CUDA/ROCm), NVMe performance tuning, SR-IOV NIC virtualization, and DPDK kernel-bypass networking.
What It Defines
Defines the point-to-point serial bus interconnect for peripheral devices: physical layer (PAM4 signaling at 64 GT/s per lane in PCIe 6.0), data link layer (TLP/DLLP packet formats, ACK/NAK retry), transaction layer (memory read/write, I/O, configuration, message TLPs), PCIe configuration space (PCI-compatible + extended), MMIO BAR mapping, power management (ASPM L0s/L1, D0–D3 device states), and hot-plug/hot-swap protocols. Underpins GPUs, NVMe SSDs, NICs, FPGAs, and virtually all discrete peripherals.
Canonical (Normative)
Convenient (Practical)
Industry consortium (Intel, AMD, NVIDIA, ARM, Broadcom, Marvell, Qualcomm) that owns and maintains the PCI Express (PCIe) specification. PCIe is the universal high-speed serial bus for GPUs, NVMe SSDs, NICs, FPGAs, and virtually all discrete peripherals. PCIe 6.0 (2021) achieves 64 GT/s per lane. Membership required for normative spec access.
Related Specs
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